Search Results
Found 189 matches.
A Combined BEM/FEM Method for IC Substrate Modeling,
E. Schrik,
PhD Thesis, TU Delft, Dept. EEMCS, September, 2006.
[PDF]
Trade-offs in buffer planning,
G. Garcea,
PhD Thesis, TU Delft, Dept. EEMCS, ISBN 90-809648-3-2, June, 2005.
[PDF]
An Efficient Method for Substrate Impedance Extraction,
Q. Wang and N. P. van der Meijs,
in Conference on PhD Research In Microelectronics and Electronics (PRIME 2005), Lausanne, CH, July, 2005.
[PDF]
Throughput driven unidirectional bus design for NoC applications,
G. Garcea and N. P. van der Meijs,
in Proc. ProRISC 2004 Benelux Workshop on Circuits, Systems and Signal Processing, pp. 391-397, Veldhoven, November, 2004.
[PDF]
Statistically aware buffer planning,
G. S. Garcea and N. P. van der Meijs and K. J. van der Kolk and R. H. M. J. Otten,
in DATE 04, pp. 1402-1403, Paris, February, 2004.
[PDF]
Combined BEM/FEM vs. 3D FEM substrate resistance modeling,
E. Schrik and N. P. van der Meijs,
in Proc. ProRISC 2004 Benelux Workshop on Circuits, Systems and Signal Processing, pp. 435-441, Veldhoven, November, 2004.
[PDF]
Substrate resistance modeling by combination of BEM and FEM methodologies,
E. Schrik and N. P. van der Meijs,
in W. Schilders e.a. (ed.), Scientific computing in electrical engineering, Springer, pp. 364-372, Heidelberg, 2004.
[PDF]
SPACE for Substrate Resistance Modeling,
N. P. van der Meijs,
in S. Donnay and G. Gielen (ed.), Substrate Noise Coupling in Mixed-Signal ASIC's, Kluwer, pp. 65-92, ISBN 1-420-7381-X, 2003.
[PDF]
Analytic Model for Area-Constrained Optimal Repeater Insertion,
G. S. Garcea N. P. van der Meijs and R. H. J. M. Otten,
in Proc. of the 7th IEEE Workshop on Signal Progation on Interconnects, pp. 127-130, Siena, IT, 2003.
[PDF]
Analytic Model for Area and Power Constrained Optimal Repeater Insertion,
G. S. Garcea N. P. van der Meijs and R. H. J. M. Otten,
in Proc. of the 29th European Solid-State Circuits Conf., pp. 591-594, Estoril, Portugal, 2003.
[PDF]
Simultaneous Analytic Area and Power Optimization for Repeater Insertion,
G. S. Garcea N. P. van der Meijs and R. H. J. M. Otten,
in Proc. of the International Conf. on Computer Aided Design, pp. 568-573, San Jose, CA, USA, 2003.
[PDF]
Comparing Two Y$\Delta$ Based Methodologies for Realizable Model Reduction,
E. Schrik and N. P. van der Meijs,
in ProRISC IEEE 14th Annual Workshop on Circuits, Systems and Signal Processing, pp. 148-152, November, 2003.
[PDF]
Coherent Interconnect/Substrate Modeling Using SPACE - An Experimental Study,
E. Schrik and A. J. van Genderen and N. P. van der Meijs,
in Proc. of the 33rd European Solid-State Device Research Conf., pp. 585-588, Estoril, Portugal, September, 2003.
[PDF]
Buffer Planning for Global Wires Under Statistical Process Vatiations,
G. S. Garcea N. P. van der Meijs and R. H. J. M. Otten,
in ProRISC IEEE 14th Annual Workshop on Circuits, Systems and Signal Processing, pp. 64-69, November, 2003.
[PDF]
Partial Inductance Extraction with an Exponentially Damped Potential Compared to Virtual Screening,
A. J. Dammers and N. P. van der Meijs,
in Proc. 6th IEEE workshop on Signal Propagation on Interconnects, pp. 29-32, Castelvecchio Pascoli - Pisa, Italy, May, 2002.
[PDF] [presentation PDF]
Large Model Reduction for VLSI Physical Verification,
N. P. van der Meijs,
in Proc. URSI General Assembly 2002, Maastricht, NL, August, 2002.
[PDF] [presentation PDF] [handout PDF]
Combined BEM/FEM Substrate Resistance Modeling,
E. Schrik and N. P. van der Meijs,
in Proc. 39th Design Automation Conference, pp. 771-776, New Orleans, LA, August, 2002.
[PDF]
Theoretical and Practical Validation of Combined BEM/FEM Substrate Resistance Modeling,
E. Schrik and P. M. Dewilde and N. P. van der Meijs,
in Proc. Int. Conf. on Computer-Aided Design, pp. 10-15, November, 2002.
[PDF]
Design and Implementation of a Technology File Interface for SPACE,
X. Burgerhout,
Delft, The Netherlands, January, 2001.
[PDF]
Design and Implementation of a Technology File Interface for SPACE,
X. Burgerhout,
Delft, The Netherlands, January, 2001.
[PDF]
Morpheus: A Tool for Generation of Schematics of Extracted Transistor Level Circuits with Parasitics Components,
A. J. van Rhijn,
Delft, The Netherlands, January, 2001.
[PDF]
Morpheus: A Tool for Generation of Schematics of Extracted Transistor Level Circuits with Parasitics Components,
A. J. van Rhijn,
Delft, The Netherlands, January, 2001.
[PDF]
Are Wires Plannable?,
R. H. J. M. Otten and G. S. Garcea,
in Proc. Int. Workshop on System-Level Interconnect Prediction, pp. 59-66, Sonoma, California, March, 2001.
[PDF]
Modeling Capactive Effects via the Substrate,
A. J. van Genderen and N. P. van der Meijs and E. Schrik,
in ProRISC IEEE 12th Annual Workshop on Circuits, Systems and Signal Processing, pp. 366-370, November, 2001.
[PDF]
Combined BEM/FEM Resistance Modeling of Stratified Substrates with Layout-Dependent Doping Patterns in the Top Layer,
E. Schrik and A. J. van Genderen and N. P. van der Meijs,
in ProRISC IEEE 12th Annual Workshop on Circuits, Systems and Signal Processing, pp. 598-604, November, 2001.
[PDF]
Assessment of 3D Interconnect Geometry at the System Level,
G. S. Garcea and N. P. van der Meijs,
in ProRISC IEEE 12th Annual Workshop on Circuits, Systems and Signal Processing, pp. 361-365, November, 2001.
[PDF]
SPACE Layout-to-Circuit Extractor Release Notes Version 4.10,
A. J. van Genderen and S. de Graaf and N. P. van der Meijs,
p. 5, Report to OptEM, December, 2001.
[PDF]
SPOCK Configuration Language Reference Manual,
X. Burgerhout and S. de Graaf and N. P. van der Meijs,
p. 45, Report to OptEM, December, 2001.
[PDF]
The Bi-Resolution Approach to Capacitance Extraction,
E. Schrik,
Delft, The Netherlands, January, 2000.
[PDF]
The Bi-Resolution Approach to Capacitance Extraction,
E. Schrik,
Delft, The Netherlands, April, 2000.
[PDF]
SPACE Layout-to-Circuit Extractor Release Notes Version 4.8,
A. J. van Genderen and S. de Graaf and N. P. van der Meijs,
p. 5, March, 2000.
[PDF]
SPACE Layout-to-Circuit Extractor Release Notes Version 4.9,
A. J. van Genderen and S. de Graaf and N. P. van der Meijs,
October, 2000.
[PDF]
Modeling and Determination of Parasitics in Submicron VLSI Layouts,
Nick van der Meijs and Arjan van Genderen and Giuseppe Garcea and Simon de Graaf and Patrick Dewilde,
Delft, The Netherlands, October, 1999.
[PDF]
Virtual Screening: A Step Towards a Sparse Partial Inductance Matrix,
A. J. Dammers and N. P. van der Meijs,
in Proc. Int. Conf. on Computer-Aided Design, pp. 445-552, San Jose, California, November, 1999.
[PDF]
Deep-Submicron ULSI Parasitics Extraction Using Space,
F. Beeftink and A. J. van Genderen and N. P. van der Meijs and J. Poltz,
in Design, Automation and Test in Europe Conference 1998, Designer Track, pp. 81-86, February, 1998.
[PDF]
An Improved Method to Extract the Capacitances of an Integrated Circuit,
W. van Til,
Delft, The Netherlands, June, 1998.
[PDF]
Towards a Sparse Partial Inductance Matrix,
A. J. Dammers and N. P. van der Meijs,
in ProRISC CSSP98, pp. 93-99, Mierlo, The Netherlands, November, 1998.
[PDF]
Gate-Size Selection for Standard Cell Libraries,
F. Beeftink and P. Kudva and D. S. Kung and L. Stok,
in Proc. Int. Conf. on Computer-Aided Design, pp. 545-550, San Jose, California, November, 1998.
[PDF]
Space Tutorial -- Helios Version,
S. de Graaf and N. P. van der Meijs and A. J. van Genderen,
Delft, The Netherlands, November, 1998.
[Link]
Hybrid Models for Parasitic Capacitances in Advanced VLSI Circuits,
E. B. Nowacka,
PhD Thesis, Delft University of Technology, Delft, The Netherlands, January, 1997.
[PDF]
Cartesian Multipole Based Numerical Integration for 3D Capacitance Extraction,
U. Geigenmuller and N. P. van der Meijs,
in European Design and Test Conference, pp. 256-259, March, 1997.
[PDF]
Evaluation and Comparison of the Space Layout-to-Circuit Extractor,
P. J. H. Elias and N. P. van der Meijs,
Delft, The Netherlands, April, 1997.
Space Features and Performance Summary,
F. Beeftink and A. J. van Genderen and N. P. van der Meijs,
Delft, The Netherlands, September, 1997.
[PDF]
Hybrid Models for Parasitic Capacitances in Advanced VLSI Circuits,
E. B. Nowacka,
Delft, The Netherlands, January, 1997.
Incorporating Support for 45 Degrees Layouts and Other Changes to Space,
F. V. Fjeld,
Delft, The Netherlands, July, 1997.
[PDF]
Advanced Subgraph Isomorphism for the Identification of Complex Device Structures.,
F. Beeftink,
Delft, The Netherlands, 1997.
[PDF]
Review of Discretization Methods for the Semiconductor Equations.,
F. Beeftink,
Delft, The Netherlands, 1997.
[PDF]
Equivalent Circuits for Semiconductor Device Modeling.,
F. Beeftink,
Delft, The Netherlands, 1997.
[PDF]
Modeling Substrate Coupling Effects using a Layout-to-Circuit Extraction Program,
Arjan van Genderen and Nick van der Meijs,
in ProRISC IEEE 8th Annual Workshop on Circuits, Systems and Signal Processing, pp. 193-200, November, 1997.
[PDF]
Combining Subgraph Isomorphism and Hashing Techniques for Efficient Bipolar Layout-to-Circuit Extraction,
F. Beeftink and N. P. van der Meijs,
Delft, The Netherlands, January, 1996.
[PDF]
Including Higher-Order Moments of RC Interconnections in Layout-to-Circuit Extraction,
P. J. H. Elias and N. P. van der Meijs,
in Proc. European Design and Test Conf., pp. 362-366, Paris, France, March, 1996.
[PDF]
Fast Computation of Substrate Resistances in Large Circuits,
A. J. van Genderen and N. P. van der Meijs and T. Smedes,
in Proc. European Design and Test Conf., pp. 560-565, Paris, France, March, 1996.
[PDF]
The Hybrid Element Method for EMC Problems in VLSI Circuits,
E. B. Nowacka and N. P. van der Meijs and P. Dewilde,
in Proc. 3rd Int. Conf. on Computation in Electromagnetics, pp. 72-77, Bath, UK, April, 1996.
[PDF]
The Hybrid Element Method for Capacitance Extraction in a VLSI Layout Verification System,
E. B. Nowacka and N. P. van der Meijs,
in P. P. Silvester (ed.), Software for Electrical Engineering Analysis and Design (Proc. ELECTROSOFT '96), Computational Mechanics Publications, pp. 125-134, Pisa, Italy, May, 1996.
[PDF]
Simulation of Power-On Node Initialization in a Switch-Level Network,
A. J. van Genderen,
Delft, The Netherlands, 1996.
[PDF]
Efficient Moments Extraction of Large Inductively Coupled Interconnection Networks,
P. J. H. Elias and N. P. van der Meijs,
in Proc. Int. Symp. on Circuits and Systems, pp. IV 540-543, Atlanta, Georgia, May, 1996.
[PDF]
Circuit Models for the Hybrid Element Method,
P. M. Dewilde and E. B. Nowacka,
in Proc. Int. Symp. on Circuits and Systems, pp. IV 616-619, Atlanta, Georgia, May, 1996.
[PDF] [poster part A PDF] [poster part B PDF]
A Hybrid Element Method for Calculation of Capacitances from the Layout of Integrated Circuits,
E. B. Nowacka and P. Dewilde and T. Smedes,
in R. C. Ertekin and C. A. Brebbia and M. Tanak and R. Shaw (ed.), Boundary Element Technology XI (Proc BETECH 96), Computational Mechanics Publications, pp. 415-425, Hawai, U.S.A., May, 1996.
[PDF]
Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction,
A. J. van Genderen and N. P. van der Meijs,
in Proc. 33rd Design Automation Conf., pp. 758-763, Las Vegas, Nevada, June, 1996.
[PDF]
Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency,
P. J. H. Elias and N. P. van der Meijs,
in Proc. 33rd Design Automation Conf., pp. 764-769, Las Vegas, Nevada, June, 1996.
[PDF]
Xspace User's Manual,
A. J. van Genderen and N. P. van der Meijs,
Delft, The Netherlands, August, 1996.
[Link]
Space Substrate Resistance Extraction User's Manual,
A. J. van Genderen and N. P. van der Meijs and T. Smedes,
Delft, The Netherlands, August, 1996.
[Link]
SWITCH: Space's integrated User Interface within a Cadence Design Environment,
M. S. Sneeuw,
Delft, The Netherlands, September, 1996.
[PDF]
Multipole Acceleration of Numerical Integration in the Boundary Element Method for 3D Capacitance Extraction,
U. Geigenmuller and N. P. van der Meijs,
in Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing, pp. 143-148, November, 1996.
[PDF]
Matrix Reduction in IC and PCB Parasitics Extraction Programs,
P. J. H. Elias and G. P. J. F. M. Maas,
in Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing, pp. 125-130, Mierlo, The Netherlands, November, 1996.
[PDF]
Deep Submicron Verification,
N. P. van der Meijs,
in Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing, pp. 391-392, Mierlo, The Netherlands, November, 1996.
[PDF]
Accurate Interconnect Modeling: Towards Multi-million Transistor Chips As Microwave Circuits,
N. P. van der Meijs and T. Smedes,
in Proc. Int. Conf. on Computer-Aided Design, pp. 244-251, San Jose, California, November, 1996.
[PDF] [slides PDF]
Space User's Manual, Space Tutorial, Space 3D Capacitance Extraction User's Manual,
A. J. van Genderen and N. P. van der Meijs,
Delft, The Netherlands, 1995.
[Link]
New methods for Calculation of Substrate Coupling for Layout Verification,
T. Smedes,
Delft, The Netherlands, 1995.
An analytical model for the non-quasi-static small-signal behaviour of submicron MOSFETs,
T. Smedes and F. M. Klaassen,
in Solid State Electronics, pp. 121-130, 1995.
[PDF]
Network Initialization in a Switch-Level Simulator,
A. J. van Genderen,
in Proc. European Design and Test Conf., p. 596, Poster presentation, Paris, France, 1995.
[PDF]
Bipolar Device Modeling for VLSI Layout Verification,
F. Beeftink,
in Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing, pp. 15-24, Mierlo, The Netherlands, March, 1995.
[PDF] [poster PDF]
SPACE: An Accurate Layout-to-Circuit Extractor for High-Speed MOS and Bipolar Circuits,
A. J. van Genderen and N. P. van der Meijs and F. Beeftink,
in Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing, pp. 97-106, Mierlo, The Netherlands, March, 1995.
[PDF] [poster PDF]
Efficient Moments Extraction from VLSI Interconnections,
P. J. H. Elias,
in Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing, pp. 83-90, Mierlo, The Netherlands, March, 1995.
[PDF]
A Boundary Element Method for Substrate Cross-talk Analysis,
T. Smedes,
in Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing, pp. 285-294, Mierlo, The Netherlands, March, 1995.
[PDF]
Delayed Frontal Solution for Finite-Element based Resistance Extraction,
N. P. van der Meijs and A. J. van Genderen,
in Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing, pp. 195-202, Mierlo, The Netherlands, March, 1995.
[PDF] [poster PDF]
Efficient Bipolar/BiCMOS Extraction Algorithms Based on Subgraph Isomorphism,
F. Beeftink and N. P. van der Meijs,
Delft, The Netherlands, August, 1995.
[PDF]
Methods for Substrate Crosstalk Verification,
A. J. van Genderen,
Presentation at Cadence Design Systems, San Jose, California, June, 1995.
Delayed Frontal Solution for Finite-Element based Resistance Extraction,
N. P. van der Meijs and A. J. van Genderen,
in Proc. 32nd Design Automation Conf., pp. 273-278, San Francisco, California, June, 1995.
[PDF]
Layout Extraction of 3D Models for Interconnect and Substrate Parasitics,
T. Smedes and N. P. van der Meijs and A. J. van Genderen and P. J. H. Elias and R. R. J. Vanoppen,
in Proc. ESSDERC, The Hague, The Netherlands, September, 1995.
[PDF]
Accurate and Efficient Layout-to-Circuit Extraction for High-Speed MOS and Bipolar/BiCMOS Integrated Circuits,
F. Beeftink and A. J. van Genderen and N. P. van der Meijs,
in Proc. IEEE Int. Conf. on Computer Design, pp. 360-365, Austin, Texas, October, 1995.
[PDF]
Extraction of Circuit Models for Substrate Cross-talk,
T. Smedes and N. P. van der Meijs and A. J. van Genderen,
in Proc. Int. Conf. on Computer-Aided Design, pp. 199-206, San Jose, California, November, 1995.
[PDF]
Five Dutch PIONIER researchers,
February, 1994.
Space Release Notes of 24-2-1994,
N. P. van der Meijs and A. J. van Genderen,
Delft, The Netherlands, February, 1994.
[Link]
Cylinder Symmetrical Green's Functions for Substrate Resistance Calculations with the Boundary Element Method,
J. Nieuwstad,
Delft, The Netherlands, March, 1994.
[PDF]
Efficiënte Modellering van complexe VLSI Systemen,
N. P. van der Meijs,
Presentation at NWO Symposium, May, 1994.
Integrating Device Model Parameter Computation into Bipolar/BiCMOS Circuit Extraction,
F. Beeftink and A. J. van Genderen and N. P. van der Meijs,
Delft, The Netherlands, April, 1994.
[PDF]
Influence of Channel Series Resistances on Dynamic MOSFET Behaviour,
T. Smedes and F. M. Klaassen,
in Solid State Electronics, pp. 251-254, 1994.
[PDF]
Boundary Element Methods for 3D Capacitance and Substrate Resistance Calculations in Inhomogeneous Media in a VLSI Layout Verification Package,
T. Smedes and N. P. van der Meijs and A. J. van Genderen,
in Advances in Engineering Software, pp. 19-27, 1994.
[PDF]
VLSI Modeling and Verification,
A. J. van Genderen and N. P. van der Meijs,
World Wide Web home page of the modeling and verification project, available at URL http://cas.et.tudelft.nl/space, May, 1994.
[Link]
Space 3D Capacitance Extraction User's Manual,
A. J. van Genderen and N. P. van der Meijs,
Delft, The Netherlands, August, 1994.
[Link]
An Analytical Model for the Non-Quasi-Static Small-Signal Behaviour of Submicron MOSFETs,
T. Smedes and F. M. Klaassen,
in accepted for publication in Solid State Electronics, 1994.
Determining VLSI Capacitances with a Hierarchical Boundary-Element Method,
A. J. van Genderen and N. P. van der Meijs,
in Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing, pp. 51-56, Houthalen, Belgium, March, 1993.
[PDF]
Parasitics in VLSI Circuits and the Role of Layout Verification,
N. P van der Meijs and A. J. van Genderen and T. Smedes,
in Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing, pp. 77-82, Houthalen, Belgium, March, 1993.
[PDF] [poster PDF]
Extraction of Bipolar Devices from Their Mask Layout,
F. Beeftink and N. P van der Meijs,
in Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing, pp. 121-126, Houthalen, Belgium, March, 1993.
[PDF] [poster PDF]
Substrate Resistance Extraction for Physics-based Layout Verification,
T. Smedes,
in Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing, pp. 101-106, Houthalen, Belgium, March, 1993.
[PDF]
Boundary Element Methods for Capacitance and Substrate Resistance Calculations in a VLSI Layout Verification Package,
T. Smedes and N. P. van der Meijs and A. J. van Genderen,
in P. P. Silvester (ed.), Software Applications in Electrical Engineering, Computational Mechanics Publications, pp. 337-344, Southampton, England, July, 1993.
[PDF]
Hierarchical Extraction of 3D Interconnect Capacitances in large Regular VLSI Structures,
A. J. van Genderen and N. P. van der Meijs,
in Proc. IEEE Int. Conf. on Computer-Aided Design, pp. 764-769, Santa Clara, California, November, 1993.
[PDF]
Modeling and Verification of Advanced Integrated Systems,
N. P. van der Meijs and A. J. van Genderen and E. B. Nowacka and T. Smedes,
Poster Presentation, FOM Scientific Meeting, Veldhoven, The Netherlands, November, 1993.
[PDF]
Sea-of-Gates Module Generation with Orca,
N. P. van der Meijs,
Poster Presentation, FOM Scientific Meeting, Veldhoven, The Netherlands, November, 1993.
[PDF]
Experiences with the Boundary Element Method for Substrate Resistance Calculations,
T. Smedes and F. Beeftink,
Poster Presentation, FOM Scientific Meeting, Veldhoven, The Netherlands, November, 1993.
[PDF]
Determining Parasitic Capacitances Using the Hybrid Finite Element Method,
E. B. Nowacka and P. M. Dewilde,
Poster Presentation, FOM Scientific Meeting, Veldhoven, The Netherlands, November, 1993.
Efficiënte Modellering van Complexe VLSI Systemen,
N. P. van der Meijs,
in Onderzoek Berichten (NWO Nieuwsbrief), p. 1, November, 1993.
Accurate but Reduced Circuit Modeling of Advanced Integrated Systems,
A. J. van Genderen,
Presentation at Stanford University, November, 1993.
Bipolar Layout-to-Circuit Extraction - Concepts and Implementation,
F. Beeftink,
report 93-127, Delft, The Netherlands, December, 1993.
[PDF]
Accurate and Efficient Layout Extraction,
N. P. van der Meijs,
PhD Thesis, Delft University of Technology, Delft, The Netherlands, January, 1992.
[PDF]
Space User's Manual,
N. P. van der Meijs and A. J. van Genderen,
Delft, The Netherlands, April, 1992.
[Link]
Space Tutorial,
N. P. van der Meijs and A. J. van Genderen,
Delft, The Netherlands, April, 1992.
[Link]
Compact Modelling of the Dynamic Behaviour of submicron MOSFETs: Short channel effects and parasitic effects,
T. Smedes,
in ITG-Diskussionssitzung ``Characterisierung und Modellierung von Halbleiterbauelementen mit Sub-$\mu$m-Strukturen und/oder extrem hohen Operationsgeschwindigkeiten'', Schwäbisch Hall, Western Germany, March, 1992.
[PDF]
A New Description of Dual $\gamma$-factor Threshold Voltage with Continuous Second-order Derivative,
T. Smedes and J. A. van Steenwijk,
in Solid State Electronics, Pergamon Press, pp. 1649-1653, 1992.
[PDF]
Physics-based Circuit-level Model for Submicron CMOS,
F. M. Klaassen and R. M. D. Velghe and T. Smedes,
in Proc. ISSSE, pp. 610-614, Paris, France, 1992.
[PDF]
Space-Efficient Extraction Algorithms,
N. P. van der Meijs and A. J. van Genderen,
in Proc. IEEE 3rd European Design Automation Conf., pp. 520-524, Brussels, Belgium, March, 1992.
[PDF]
A Frontal Computation Scheme for the Schur Algorithm to Efficiently Solve Large Boundary-Element Problems,
A. J. van Genderen and N. P. van der Meijs,
in CompEuro Proc. Computer Systems and Software Engineering, pp. 568-573, The Hague, The Netherlands, May, 1992.
[PDF]
Hybrid Models for Parasitic Capacitances in Advanced VLSI Circuits,
E. B. Nowacka,
July, 1992.
Hybrid Models for Parasitic Capacitances in Advanced VLSI Circuits,
E. B. Nowacka and P. M. Dewilde,
in Proc. of the Polish-Chech-Hungarian Workshop on Circuit Theory and Applications, pp. 18-25, Kiry, Poland, September, 1992.
Layout Dependence of Bipolar Device Parameters,
F. Beeftink,
October, 1992.
[PDF]
Determining VLSI Capacitances with a Hierarchical Boundary-Element Method,
A. J. van Genderen,
Poster Presentation, FOM Scientific Meeting, Veldhoven,The Netherlands, Veldhoven, The Netherlands, November, 1992.
[poster PDF]
What Did You Really Design? - The Effect of Layout Parasitics,
N. P. van der Meijs and A. J. van Genderen,
Poster Presentation, FOM Scientific Meeting, Veldhoven, The Netherlands, November, 1992.
Layout Dependence of Bipolar Device Parameters,
F. Beeftink and N. P. van der Meijs,
Poster Presentation, FOM Scientific Meeting, Veldhoven, The Netherlands, November, 1992.
[PDF]
Green's Function Methods for Resistance Calculation,
T. Smedes,
Poster Presentation, FOM Scientific Meeting, Veldhoven, The Netherlands, November, 1992.
[PDF]
Reduced RC Models for IC Interconnections with Coupling Capacitances,
A. J. van Genderen and N. P. van der Meijs,
in Proc. IEEE 3rd European Design Automation Conf., pp. 132-136, Brussels, Belgium, March, 1992.
[PDF]
3-Dimensional Finite Element Modeling of Integrated Circuit Capacitances,
N. P. van der Meijs and A. J. van Genderen,
in E. Deprettere and A. J. van der Veen (ed.), Algorithms and Parallel VLSI Architectures, Vol A., Elsevier Science Publishers, pp. 267-276, ISBN 0 444 88827 6, 1991.
[PDF]
An Almost Linear Expected-Time Scanline Algorithm for the Contour of a Union of Polygons,
N. P. van der Meijs and A. J. van Genderen,
Delft, The Netherlands, August, 1991.
Space-Efficient Extraction Algorithms,
N. P. van der Meijs and A. J. van Genderen,
Delft, The Netherlands, August, 1991.
Reduced Models for the Behavior of VLSI Circuits,
A. J. van Genderen,
PhD Thesis, Delft University of Technology, Delft, The Netherlands, October, 1991.
[PDF]
Compact Modelling of the Dynamic Behaviour of MOSFETs,
T. Smedes,
Eindhoven, The Netherlands, 1991.
Analytical Modelling of Non-Quasi-Static Behaviour of Submicron MOSFETs,
T. Smedes and F. M. Klaassen,
in Proc. ISDRS, pp. 419-422, Charlottesville, Virginia, December, 1991.
[PDF]
Substrate Resistance Problems in VLSI Design,
T. Smedes and A. J. van Genderen and N. P. van der Meijs,
Poster Presentation, FOM Scientific Meeting, Veldhoven, The Netherlands, November, 1991.
[PDF]
An O(1)-Space Implementation of the Schur Algorithm for 3D Capacitance Modeling,
A. J. van Genderen and N. P. van der Meijs,
Poster Presentation, FOM Scientific Meeting, Veldhoven, The Netherlands, November, 1991.
Impedances of Submicron MOSFETs,
T. Smedes and F. M. Klaassen,
in Proc. 2nd ProRISC Symp. on Design Methodology, pp. 236-239, Dalfsen, The Netherlands, April, 1990.
A Charge and Capacitance Model for Modern MOSFETs,
T. Smedes and F. M. Klaassen,
in Proc. ESSDERC, pp. 141-144, Nottingham, England, September, 1990.
[PDF]
Effects of the Lightly Doped Drain Configuration on Capacitance Characteristics of Submicron MOSFETs,
T. Smedes and F. M. Klaassen,
in Technical Digest IEDM 1990, pp. 197-200, San Francisco, California, December, 1990.
[PDF]
Models for Large Integrated Circuits,
P. Dewilde and Z. Q. Ning,
Kluwer Academic Publishers, 1990.
Modeling of Distributed RC Effects in VLSI Circuits,
A. J. van Genderen and N. P. van der Meijs,
in Proc. 2nd ProRISC Symp. on Design Methodology, pp. 230-231, Dalfsen, The Netherlands, April, 1990.
[poster PDF]
VLSI Wiring Capacitance Determination,
N. P. van der Meijs and A. J. van Genderen,
in Proc. 2nd ProRISC Symp. on Design Methodology, pp. 240-241, Dalfsen, The Netherlands, April, 1990.
[poster PDF]
RC Models for VLSI Interconnections,
A. J. van Genderen and N. P. van der Meijs,
in Proc. 3rd ProRISC Symp., Veldhoven, The Netherlands, November, 1990.
3-Dimensional Finite Element Modeling of Integrated Circuit Capacitances,
N. P. van der Meijs and A. J. van Genderen,
in Proc. Int. Workshop on Algorithms and Parallel VLSI Architectures, pp. 112-116, Pont-a-Mousson, France, June, 1990.
[PDF]
The dependence of the contact resistance on layer thickness for planar contacts on thin epitaxial layers (I and II),
W. van Berlo and T. Smedes,
Stockholm, Sweden, August, 1990.
On the Existence and Construction of Solutions to the Partial Lossless Inverse Scattering Problem with Applications to Estimation Theory,
D. Alpay and P. Dewilde and H. Dym,
in IEEE Trans. on Information Theory, pp. 1184-1205, November, 1989.
An Efficient Method for Modelling VLSI Interconnections,
H. Nelis and E. Deprettere and P. Dewilde,
in Proc. ECCTD, pp. 94-98, London, 1989.
Effect of Velocity Saturation on Small Signal Behaviour of Submicron MOSFETs: Analytical Modelling and 2-D Simulations,
T. Smedes,
in Proc. ESSDERC, pp. 435-438, Berlin, Western Germany, September, 1989.
[PDF]
Accurate and Efficient Modeling of Global Circuit Behavior in VLSI Layouts,
Z. Q. Ning,
Delft, The Netherlands, April, 1989.
Sparse Approximations of Inverse Matrices,
H. Nelis,
Delft, The Netherlands, 1989.
SPACE: A Finite Element Based Capacitance Extraction Program for Submicron Integrated Circuits,
A. J. van Genderen and N. P. van der Meijs,
in W. Crans (ed.), Software Tools for Process, Device and Circuit Modelling, Boole Press, pp. 45-55, Dublin, Ireland, July, 1989.
[PDF]
An Efficient Finite Element Method for Submicron IC Capacitance Extraction,
N. P. van der Meijs and A. J. van Genderen,
in Proc. 26th Design Automation Conf., IEEE, pp. 678-681, Las Vegas, Nevada, June, 1989.
[PDF]
Space: An Efficient and Accurate Layout to Circuit Extractor,
N. P. van der Meijs and A. J. van Genderen,
in Proc. ProRISC Symp., Eindhoven, The Netherlands, June, 1989.
An Efficient Algorithm for Analysis of Non-Orthogonal Layout,
N. P. van der Meijs and A. J. van Genderen,
in Proc. Int. Symp. on Circuits and Systems, IEEE, pp. 47-52, Portland, Oregon, May, 1989.
[PDF]
New Algebraic Methods for Modeling Parasitics in Large Integrated Circuits,
P. Dewilde and E. Deprettere and H. Nelis and A. van Genderen and N. P. van der Meijs and Z. Ning,
in Proc. Int. Symp. on Circuits and Systems, IEEE, Portland, Oregon, May, 1989.
Efficient Modeling of Interconnections in a VLSI Circuit,
H. Nelis and P. Dewilde and E. Deprettere,
in Proc. Int. Symp. on Circuits and Systems, Portland, Oregon, May, 1989.
SLS: An Efficient Switch-Level Timing Simulator Using Min-Max Voltage Waveforms,
A. J. van Genderen,
in Proc. VLSI Conf., pp. 79-88, Munich, Western Germany, August, 1989.
Space: An Efficient and Accurate Layout to Circuit Extractor,
N. P. van der Meijs and A. J. van Genderen,
Poster Presentation, FOM Scientific Meeting, Veldhoven, The Netherlands, June, 1989.
[poster PDF]
Inversion of Partially Specified Matrices by Inverse Scattering,
H. Nelis and E. Deprettere and P. Dewilde,
in Operator Theory: Advances and Applications, Birkhauser Verlag, Basel, 1989.
Data Management for VLSI Design: Conceptual Modeling, Tool Integration \& User Interface,
P. van der Wolf and N. P. van der Meijs and T. G. R. van Leuken and I. Widya and P. Dewilde,
in F. J. Rammig (ed.), Proc. IFIP WG 10.2 Workshop on Tool Integration and Design Environments Nov. 1987, North-Holland, Paderborn, Western Germany, 1988.
Space: An Accurate and Efficient Extractor for Submicron Integrated Circuits,
N. P. van der Meijs and A. J. van Genderen,
in Delft Progr. Rep., pp. 260-279, Delft, The Netherlands, 1988.
[PDF]
An Introduction to the NELSIS IC Design System,
H. Cai and A. J. van Genderen and P. Groeneveld and A. van der Hoeven and A. A. J. de Lange and N. P. van der Meijs and P. van der Wolf,
Network Theory Section, Delft University of Technology, 1988.
New Algebraic Methods for Modelling Large-Scale Integrated Circuits,
P. Dewilde,
in International Journal of Circuit Theory and Applications, John Wiley & Sons, Ltd, pp. 473-503, 1988.
The Generalized Schur Algorithm: Approximation and Hierarchy,
P. Dewilde and Ed. F. Deprettere,
in Operator Theory: Advances and Applications, Birkhauser Verlag, Basel, pp. 97-116, 1988.
Approximate Inversion of Positive Definite Matrices, Specified on a Multiple Band,
H. Nelis and E. Deprettere and P. Dewilde,
in Delft Progress Report, 1988.
SLS: A Switch-Level Timing Simulator,
A. J. van Genderen,
in Delft Progr. Rep., Delft University Press, pp. 280-290, Delft, The Netherlands, 1988.
A New Approach to Analytically Solving the 2D Poisson Equation in MOSFET,
Z. Q. Ning and P. M. Dewilde and F. L. Neerhoff,
Delft, The Netherlands, 1988.
Approximate Inversion of Positive Definite Matrices, Specified on a Multiple Band,
H. Nelis and E. Deprettere and P. Dewilde,
in Proc. SPIE 88, San Diego, California, August, 1988.
Spider: Capacitance Modelling for VLSI Interconnections,
Z. Q. Ning and P. Dewilde,
in IEEE Trans. on Computer-Aided Design, pp. 1221-1228, December, 1988.
The Generalized Schur Algorithm: Roundoff Analysis, Vectorization, and an Application to VLSI Modelling,
M. L. F. Lossie,
Delft, The Netherlands, February, 1988.
An Efficient Modelling Technique for Computing the Parasitic Capacitances in VLSI Circuits,
Z. Q. Ning and P. M. Dewilde,
in Proc. Int. Symp. on Circuits and Systems, pp. 1131-1134, Helsinki, Finland, June, 1988.
Space, Makegln and Tecc,
A. J. van Genderen and N. P. van der Meijs,
Delft, The Netherlands, June, 1988.
Extracting Simple but Accurate RC Models for VLSI Interconnect,
A. J. van Genderen and N. P. van der Meijs,
in Proc. Int. Symp. on Circuits and Systems, pp. 2351-2354, Helsinki, Finland, June, 1988.
[PDF]
Principles of Open VLSI Data Management in the NELSIS Design System,
P. van der Wolf and N. P. van der Meijs and T. G. R. van Leuken and I. Widya and P. Dewilde,
in O. E. Herrmann B. J. F. van Beijnum (ed.), Lecture Notes of the NELSIS-Project, pp. 12-36, Delft, The Netherlands, March, 1988.
A Data Management Interface to Facilitate CAD/IC Software Exchanges,
N. P. van der Meijs and T. G. R. van Leuken and P. van der Wolf and I. Widya and P. Dewilde,
in Proc. IEEE Int. Conf. on Computer Design, pp. 403-406, 1987.
A Simple but Accurate Method to Compute VLSI Parasitic Capacitances,
Z. Q. Ning and P. Dewilde,
Delft, The Netherlands, May, 1987.
Approximate Inversion of Positive Matrices with Applications to Modelling,
P. Dewilde and E. Deprettere,
in Modelling, Robustness and Sensitivity Reduction in Control Systems, Springer-Verlag, pp. 211-237, 1987.
[PDF]
Extracting Simple But Accurate RC Models for VLSI Interconnects,
A. J. van Genderen and N. P. van der Meijs,
Poster presented at ICD meeting, FOM-IOP/IC meeting, 1987.
Analysis of Non-Orthogonal Layouts,
N. P. van der Meijs and A. J. van Genderen,
Poster presented at ICD meeting, FOM-IOP/IC meeting, 1987.
Spider: Capacitance Modelling for VLSI Interconnections,
Z. Q. Ning and P. Dewilde,
Delft, The Netherlands, April, 1987.
Large Scale VLSI Capacitance Modeling,
P. Dewilde and Z. Q. Ning and Ed. F. Deprettere,
Delft, The Netherlands, June, 1987.
Circuit Modeling for VLSI Layout Verification,
A. J. van Genderen,
Delft, The Netherlands, January, 1987.
Capacitance Coefficients for VLSI Multilevel Metallization Lines,
Z. Q. Ning and P. M. Dewilde and F. L. Neerhoff,
in IEEE Trans. on Electron Devices, pp. 644-649, March, 1987.
An Algorithm for Analysis of Non-Orthogonal Layout,
N. P. van der Meijs and A. J. van Genderen,
Delft, The Netherlands, November, 1987.
Extracting Simple But Accurate RC Models for VLSI Interconnect,
A. J. van Genderen and N. P. van der Meijs,
Delft, The Netherlands, October, 1987.
On the Surface Theory for MOS Structure with Piecewise Linear Profile,
Z. Q. Ning,
Delft, The Netherlands, December, 1987.
Data Management for Hierarchical and Multiview VLSI Design,
P. Dewilde and S. de Graaf and A. van der Hoeven and T. G. R. M. van Leuken and N. P. van der Meijs and J. Nusteling and T. Vogel and P. van der Wolf,
in P. Dewilde (ed.), The Integrated Circuit Design Book: Papers on VLSI Design Methodology from the ICD-NELSIS Project, Delft University Press, pp. 1.1-1.29, Delft, The Netherlands, 1986.
Procedural Layout Generation and Silicon Assembly in C,
N. P. van der Meijs,
in P. Dewilde (ed.), The Integrated Circuit Design Book: Papers on VLSI Design Methodology from the ICD-NELSIS Project, Delft University Press, pp. 1.30-1.48, Delft, The Netherlands, 1986.
Optimization and Down Scaling of Processes for Emittor Coupled Logic,
T. Smedes,
Eindhoven, The Netherlands, August, 1986.
A new Method for Determining the Resistance of VLSI Interconnect,
P. Kazil,
Delft, The Netherlands, July, 1986.
A Simple and Fast Method for Obtaining Resistance of VLSI Interconnect,
P. Kazil and P. Dewilde,
in Proc. IEEE Int. Conf on Computer Design, pp. 342-345, October, 1986.
Capacitance Coefficients for VLSI Multilevel Metallization Lines,
Z. Q. Ning and P. Dewilde and F. L. Neerhoff,
Delft, The Netherlands, 1986.
SLS: A Switch-Level Timing Simulator,
A. J. van Genderen and A. C. de Graaf,
in P. Dewilde (ed.), The Integrated Circuit Design Book, Delft University Press, pp. 2.93-2.146, Delft, The Netherlands, 1986.
Switch level timing simulation,
A. J. van Genderen,
Delft, The Netherlands, June, 1985.
Switch level timing simulation,
P. M. Dewilde and A. J. van Genderen and A. C. de Graaf,
in Proc. IEEE Int. Conf. on Computer-Aided Design, pp. 182-184, Santa Clara, California, November, 1985.
VLSI Circuit Reconstruction from Mask Topology,
N. P. van der Meijs and J. T. Fokkema,
in INTEGRATION, the VLSI Journal, pp. 85-119, 1984.
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