SPACE

Space Helios Tutorial

Welcome to this tutorial that will lead you through the amazing possibilities of Space, an accurate and efficient layout-to-circuit extractor. For this tutorial you will need Space version 4.4.4 or higher, its GUI Helios version 1.3.4 or higher (available since 15 July 1998), and the circuit simulator Spice. Space and Helios are both included in the standard CACD tree, which can be downloaded here. The program Spice can be obtained from the University of California at Berkeley.

We have done our best to make an interesting and clear tutorial. However, any suggestions for improvements can be addressed to the Space Development Team.

1. Starting with Helios

• How to start (and exit) helios.
• Have a brief look at the menus and windows.
• Load settings from "$ICDPATH/share/tutorial/helios.defaults".
• Move the QuickRef Window to another place.
• Create project "handson" (process=scmos_n with lambda=0.01).
• Save settings in your project directory.
• Copy the ".cmd" files from "$ICDPATH/share/tutorial" to your project.

2. Extraction of switchbox4

• Load settings from "$ICDPATH/share/tutorial/helios.defaults" or be sure that the options have been set (back) according to as they were directly after reading this file a previous time.
• Import the GDSII description from "switchbox4.gds" using Layout -> Import.
• Use "Database -> List" or Control+L to make a hierarchical cells listing.
• Select switchbox4 in the "List of Cells" area of the helios main window.
• Watch the layout of switchbox4 and its children using Layout -> Editor.
• Turn on verbose mode using "Extractor -> Extraction options -> Verbose".
• Extract switchbox4 hierarchically.
• Select circuit view in "List of Cells" and do Database -> List (Control+L) again.
• Circuit -> Retrieve switchbox4 with full hierarchy for spice and edif.
• Extract switchbox4 flat and type Control+L again.
• View the result: Circuit -> Retrieve switchbox4 with full hierarchy for spice.
• Run Circuit -> Simeye with sls-logic on switchbox4.

3. Extraction of oscil

• Load settings from "$ICDPATH/share/tutorial/helios.defaults" or be sure that the options have been set (back) according to as they were directly after reading this file a previous time.
• Import the GDSII description from "oscil.gds" (Layout -> Import).
• Select the layout cell oscil and make a Database -> List (Control+L).
• Watch the layout of oscil and its children using Layout -> Editor.
• Select the circuit view, Extract oscil flat, and type Control+L.
• Run Circuit -> Simeye with spice on oscil (watch frequency by counting the periods).
• Extract oscil flat with fast Cap. extraction, and type Control+L.
• Run Circuit -> Simeye with spice on oscil (watch frequency).
• Extract oscil flat with fast Cap. and fast Res. extraction, and type Control+L.
• Run Circuit -> Simeye with spice on oscil (watch frequency).
  Note the noise on "sense" because of the contact resistance. Using View -> ZoomIn it is possible to zoom in on the signal after first selecting Options -> DetailZoomON.
• Use Extractor -> Display options -> (draw tiles & draw FE mesh) to watch the FE mesh used for resistance extraction. Click on "Extract".

4. Working with Element Definition Files

• Continue with this section directly after finishing the above section.
• Copy the element definition file from "$ICDPATH/share/lib/process/scmos_n/space.def.s". to e.g. "elem.s", look at it, remove contact resistances by putting the resistivity field for the contact elements to zero. Compile the modified "elem.s" with "Database->New technology" into "elem.t" file.
  Use this customized "elem.t" file and extract oscil again.
  Run Circuit -> Simeye with spice on oscil (watch frequency).
  Note that now the noise on "sens" has disappeared and that the delay is almost equal to when only capacitances are extracted. The latter is because the total interconnect resistance was mainly determined by the contact resistance.

5. Accurate 3D Capacitance Extraction of poly5 and oscil

• Load settings from "$ICDPATH/share/tutorial/helios.defaults" or be sure that the options have been set (back) according to as they were directly after reading this file a previous time.
• Import the GDSII description from "poly5.gds".
• Select poly5 in the "List of Cells" area and watch the layout with dali.
• Perform an accurate 3D Cap. extraction. Set first "Extraction options -> Capacitance: accurate ext." and then select "Details -> {Window size: 10u, Max.BE area: 1u}" and click on "Accept". In "Extract Options" set "Circuit Reduction" to "no reduction heuristics" and click on "Accept Options". Use "Display options -> {Use Display, draw BE mesh, 3 dimensional picture, draw Green}" and click on "Extract". See the Display note.
• Look at the spice output ("Circuit -> Retrieve" or Control+R).
• Perform an accurate Cap. extraction. Set now "Capacitance Extraction" -> "Details" -> "Window size" to 1u.
• Look at the spice output again (Control+R). Because of the reduced window size, direct coupling capacitances are now only found between neighbor wires. Note that the total capacitance that is connected to a conductor is approximately unchanged. It appears that when the window size is kept constant, the extraction time is proportial to the size of the layout and the memory usage is more or less indepent of the size of the layout. Play with e.g. the window size or Max. BE area.
• Perform now an accurate Cap. extraction (Max.BE area: 1u, Window size: 3u) for cell oscil.
  Maybe first use "Display options -> BE Mesh: only drawing, no extraction".
  Then turn it OFF and also turn OFF "Display options -> BE Mesh: draw green".

6. Accurate 3D Substrate Resistance Extraction of term3

• Load settings from "$ICDPATH/share/tutorial/helios.defaults" or be sure that the options have been set (back) according to as they were directly after reading this file a previous time.
• Import the GDSII description from "term3.gds".
• Select term3 and inspect the layout with the layout editor dali.
• Perform an accurate 3D Substrate Res. extraction. Set first "Extraction options -> Substrate Resistance: accurate ext." and then select "Details -> {Window size: 10u, Max.BE area: 1u}" and click on "Accept Options" and in "Extract Options" also on "Accept Options". Use "Display options -> {Use Display, draw BE mesh, draw Green}" and click on "Extract". See the Display note.
• Look at the spice output (Control+R).
• Perform an accurate 3D Substrate Res. extraction, now with Window size: 1u.
• Look at the spice output again. Note that now no direct coupling resistances are computed because the contacts are more than 1u apart. However, the substrate contacts are still coupled to each other via the resistances to the 'SUBSTR' node.
• Perform now a fast Substrate Res. extraction. Set first Extraction options -> Substrate Resistance to "fast extraction" and click on "Accept Options". In "Display options", turn OFF all drawing options, turn OFF "Use Display", and click on "Extract".
• Look at the spice output again.

7. Fast Substrate Resistance Extraction of oscil (cont.)

• Load settings from "$ICDPATH/share/tutorial/helios.defaults" or be sure that the options have been set (back) according to as they were directly after reading this file a previous time.
• Extract oscil flat with fast Capacitance extraction, fast Interconnect Resistance extraction and fast Substrate Resistance extraction.
  - First use Extractor -> Display options -> {draw substrate terminal, draw Delaunay} to see how the extractor uses a Delaunay diagram to determine between which direct coupling resistances are computed (the resistances that are connected by at least one line of the Delaunay diagram).
  - Then use Extractor -> Display options -> {draw substrate terminal, draw substrate resistor} to actually see the direct coupling resistances that are computed.
• Run Circuit -> Simeye with spice on oscil. Note the noise on signal "sens" because of the influence of the substrate resistances. Recall that using View -> ZoomIn it is possible to zoom in on a signal after first selecting Options -> DetailZoomON.
• Create with Layout -> Editor an extra substrate contact with mask "cca" on the "vss" wire near contact "sens" and write the cell back to the database.
• Extract oscil again (Control+E).
• Run Circuit -> Simeye with spice on oscil and note the reduced noise.

8. RC Model Extraction of RC

• Load settings from "$ICDPATH/share/tutorial/helios.defaults" or be sure that the options have been set (back) according to as they were directly after reading this file a previous time.
• Import the GDSII description from "RC.gds".
• Watch the layout of RC with dali. It consists of a polysilicon resistor and a poly - metal capacitor in series.
• Set "Extractor -> Extraction options -> Circuit Reduction" to "no reduction heuristics"
• Extract Interconnect Resistances with Mode "fast" and Capacitances with Mode "fast" and Type "cap's to substrate, vertical and lateral coupling cap's".
• Retrieve a spice netlist in file "RC_0.spc":
  Set "Retrieval options -> Advanced Options -> Misc. Options -> Use control file" to "$ICDPATH/share/tutorial/xspicerc_notitle".
  Set "Retrieval options -> Output to file" to "RC_0.spc" and click "Retrieve".
• Extract again, but use "frequency dependent" circuit reduction with max. is 0.1 GHz.
• Retrieve again: Set "Retrieval options -> Output to file" to "RC_100M.spc".
• Extract again: Set max. freq. to 1 GHz.
• Retrieve again: Set "Retrieval options -> Output to file" to "RC_1G.spc".
• Extract again: Set max. freq. to 100 GHz.
• Retrieve again: Set "Retrieval options -> Output to file" to "RC_100G.spc".
• Copy "$ICDPATH/share/tutorial/RC_master.spc" to your project directory and view the file to verify that it includes the extracted circuits. Use a terminal window!
• Simulate this four extracted circuits using the command "spice3 RC_master.spc" or any similar command that is appropriate for your Spice installation. Note that - when it is assumed that the results for the circuit "RC_100G.spc" are most accurate - the approximation of the magnitude and the phase gradually improves as the maximum frequency for circuit reduction becomes higher. Exit spice3 with the "quit" command.

9. Extraction of the CORDIC Chip P505

• Load settings from "$ICDPATH/share/tutorial/helios.defaults" or be sure that the options have been set (back) according to as they were directly after reading this file a previous time.
• Create a new project "p505" (process=c3tu with lambda=0.15).
• Import the GDSII description from "P505.gds".
• Watch the layout of P505 with dali.
• Make a hierarchical cells listing of P505 (select cell P505 and type Control+L).
• Extract P505 flat, with Capacitance to "fast extraction", Type is "capacitances to substrate" and verbose is ON (use "no extraction" for Interconnect Resistance).
• Make a hierarchical cells listing of P505 and watch the circuit view.

For questions about Space/Helios: Space Development Team