Mission
The continuously decreasing dimensions of the features assembled on
advanced integrated circuits and systems, together with more ambitious
design styles (such as combined Analog/Digital chips and clock
frequencies in the GHz-range) mandate a level of understanding,
modeling and verification of various (parasitic) physical/electrical
phenomena that exceeds by far the current state-of-the-art. We intend
to bridge this knowledge gap.
In particular, the objectives of our research are concerned with
answering the following questions that become ever more important
because of the on-going increase of VLSI integration density:
- What are the most important global parasitic effects in a
submicron VLSI chip and in what manner can these effects be described
mathematically?
- How do we attain reliable models for these phenomena?
- In what manner is it possible to extract these models from the
description of the technology and the layout of the chip?
- How can a designer verify her design and check its correct
functioning in the presence of these phenomena?
- In what manner can a designer be supported in an optimal fashion?
In more concrete terms, we are working on the following subjects (a
brief and non-complete listing):
- Accurate modeling and extraction of interconnect resistance,
capacitance, inductance.
- Modeling of the substrate (crosstalk via the substrate).
- Extraction of full-custom bipolar and BiCMOS layouts, including
accurate modeling of the bipolar devices.
- Model reduction.
Keywords and concepts that guide our research are:
- accuracy
- efficiency
- usefulness
- feedback from users and industry in general
- Verify and enhance our knowledge through prototype
implementations in Space.
Many of the knowledge that we develop is tested and implemented in our
layout-to-circuit extractor called Space.
We keep many of our papers on-line, they can be obtained by clicking here.
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